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1.92
 
1.93
 
MAIN:ragge:20040515080617
 
reader.c
_>11721172 
 11731173                 tl = istnode(p->n_left);
 11741174                 tr = istnode(p->n_right);
<>1175 -                is3 = ((q->needs & (NDLEFT|NDRIGHT)) == 0);
  1175+                is3 = ((q->rewrite & (RLEFT|RRIGHT)) == 0);
11761176 
 11771177                 if (shl && shr) {
 11781178                         int got = 10;
     
 !
11831183                          * there is a 3-op instruction that ends in a reg,
 11841184                          * be quite happy. If neither, cannot do anything.
 11851185                          */
<>1186 -                        if (tl && (q->needs & NDLEFT)) {
  1186+                        if (tl && (q->rewrite & RLEFT)) {
11871187                                 got = 1;
<>1188 -                        } else if (tr && (q->needs & NDRIGHT)) {
  1188+                        } else if (tr && (q->rewrite & RRIGHT)) {
11891189                                 got = 1;
<>1190 -                        } else if ((q->needs & (NDLEFT|NDRIGHT)) == 0) {
  1190+                        } else if ((q->rewrite & (RLEFT|RRIGHT)) == 0) {
11911191                                 got = 3;
 11921192                         }
 11931193                         if (got < mtchno) {
     
 !
12041204                          * a temporary register, and the current op matches,
 12051205                          * be happy.
 12061206                          */
<>1207 -                        if ((q->needs & NDRIGHT) && istnode(r)) {
  1207+                        if ((q->rewrite & RRIGHT) && istnode(r)) {
12081208                                 /* put left in temp, add to right */
 12091209                                 if (4 < mtchno) {
 12101210                                         mtchno = 4;
 12111211                                         rv = MKIDX(ixp[i], LREG);
 12121212                                 }
<>1213 -                        } else if (q->needs & NDLEFT) {
  1213+                        } else if (q->rewrite & RLEFT) {
12141214                                 if (4 < mtchno) {
 12151215                                         mtchno = 4;
 12161216                                         rv = MKIDX(ixp[i], LREG);
     
 !
12311231                          * a temporary register, and the current op matches,
 12321232                          * be happy.
 12331233                          */
<>1234 -                        if ((q->needs & NDLEFT) && istnode(l)) {
  1234+                        if ((q->rewrite & RLEFT) && istnode(l)) {
12351235                                 /* put right in temp, add to left */
 12361236                                 if (4 < mtchno) {
 12371237                                         mtchno = 4;
 12381238                                         rv = MKIDX(ixp[i], RREG);
 12391239                                 }
<>1240 -                        } else if (q->needs & NDRIGHT) {
  1240+                        } else if (q->rewrite & RRIGHT) {
<_12411241                                 if (4 < mtchno) {
 12421242                                         mtchno = 4;
 12431243                                         rv = MKIDX(ixp[i], RREG);
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Atlassian FishEye, CVS analysis. (Version:1.6.3 Build:build-336 2008-11-04) - Administration - Page generated 2014-12-25 11:46 +0100